Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
betaFALSE build_version2405991
date_generatedTue Oct 15 17:12:12 2024 os_platformWIN64
product_versionVivado v2018.3 (64-bit) project_ida49c2cf7d94c486e81d5b7db0637ee28
project_iteration1 random_id5ef4283a661a5c36860b7fb516ade6b0
registration_id5ef4283a661a5c36860b7fb516ade6b0 route_designTRUE
target_devicexc7s6 target_familyspartan7
target_packageftgb196 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i5-6300HQ CPU @ 2.30GHz cpu_speed2304 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram17.000 GB total_processors1

vivado_usage
gui_handlers
addsrcwizard_specify_hdl_netlist_block_design=1 addsrcwizard_specify_or_create_constraint_files=1 basedialog_cancel=1 basedialog_ok=6
basedialog_yes=3 constraintschooserpanel_add_files=1 filesetpanel_file_set_panel_tree=15 flownavigatortreepanel_flow_navigator_tree=6
fpgachooser_fpga_table=1 gettingstartedview_create_new_project=1 msgtreepanel_message_view_tree=12 netlistschematicview_show_io_ports_in_this_schematic=1
pacommandnames_add_sources=2 pacommandnames_run_bitgen=1 paviews_code=1 projectnamechooser_choose_project_location=2
projectnamechooser_project_name=1 projecttab_reload=3 rungadget_show_warning_and_error_messages_in_messages=3 saveprojectutils_save=1
signaltablepanel_signal_table=1 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1
java_command_handlers
addsources=2 newproject=1 runbitgen=3 runschematic=1
runsynthesis=1 showview=5
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=1 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=1 carry4=5 fdce=20 fdpe=15
fdre=4 gnd=1 ibuf=2 lut1=1
lut2=1 lut3=16 lut4=7 lut6=21
obuf=16 vcc=1
pre_unisim_transformation
bufg=1 carry4=5 fdce=20 fdpe=15
fdre=4 gnd=1 ibuf=2 lut1=1
lut2=1 lut3=16 lut4=7 lut6=21
obuf=16 vcc=1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
timing-17=39

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") confidence_level_clock_activity=Low confidence_level_design_state=High
confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Low confidence_level_overall=Low
customer=TBD customer_class=TBD devstatic=0.019847 die=xc7s6ftgb196-1
dsp_output_toggle=12.500000 dynamic=0.311355 effective_thetaja=3.4 enable_probability=0.990000
family=spartan7 ff_toggle=12.500000 flow_state=routed heatsink=medium (Medium Profile)
i/o=0.004020 input_toggle=12.500000 junction_temp=26.1 (C) logic=0.152399
netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=0.331202 output_enable=1.000000
output_load=5.000000 output_toggle=12.500000 package=ftgb196 pct_clock_constrained=0.000000
pct_inputs_defined=0 platform=nt64 process=typical ram_enable=50.000000
ram_write=50.000000 read_saif=False set/reset_probability=0.000000 signal_rate=False
signals=0.154936 simulation_file=None speedgrade=-1 static_prob=False
temp_grade=commercial thetajb=13.7 (C/W) thetasa=15.4 (C/W) toggle_rate=False
user_board_temp=25.0 (C) user_effective_thetaja=3.4 user_junc_temp=26.1 (C) user_thetajb=13.7 (C/W)
user_thetasa=15.4 (C/W) vccadc_dynamic_current=0.000000 vccadc_static_current=0.000000 vccadc_total_current=0.000000
vccadc_voltage=1.800000 vccaux_dynamic_current=0.000001 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.007102 vccaux_total_current=0.007103
vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000 vccbram_static_current=0.000060 vccbram_total_current=0.000060
vccbram_voltage=1.000000 vccint_dynamic_current=0.311335 vccint_static_current=0.003703 vccint_total_current=0.315038
vccint_voltage=1.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000
vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000
vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000
vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000
vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000
vcco25_voltage=2.500000 vcco33_dynamic_current=0.000006 vcco33_static_current=0.001000 vcco33_total_current=0.001006
vcco33_voltage=3.300000 version=2018.3

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7s6ftgb196-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=seg -verilog_define=default::[not_specified]
usage
elapsed=00:00:26s hls_ip=0 memory_gain=463.184MB memory_peak=783.879MB